1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same by which it is possible to prevent galvanic corrosion from occurring in a dual metal gate structure.
2. Description of the Related Art
Transistors with a higher degree of integration and a higher operating speed have been realized by miniaturization of the transistors, based on the scaling rule. Thinning of the gate insulation film has progressed, and in a transistor of a gate length of, for example, 0.1 μm or less, it may be necessary to reduce the thickness of the gate insulation film to or below 2 nm.
As a gate electrode material, normally, polycrystalline Si (polysilicon) is used. The reasons for this include the stability of the interface between the gate electrode and the gate insulation film beneath the gate electrode. Another reason lies in that, since an impurity can be easily introduced into the inside of polysilicon by such techniques as ion implantation and diffusion, it is possible to obtain an optimum threshold by forming gate electrodes with optimum work functions for nMOS and pMOS through appropriately selecting the impurity element and the concentration thereof.
However, attendant on the miniaturization of transistors, the problem of depletion of the gate electrode has become conspicuous. The depletion of the gate electrode is a phenomenon which is difficult to restrain, because polysilicon is a semiconductor. In view of this, it has been widely reported that the depletion of the gate electrode can be restrained by forming a film of a metal, in place of polysilicon, directly on the gate insulation film, and attention has therefore been paid to the development of a metal gate.
However, in the case where the metal gate is composed of a single kind of metal, the work function of the gate electrode for an nMOS transistor and that for a pMOS transistor are equal to each other. Therefore, it is difficult to regulate the work function of the gate electrode for the nMOS transistor and the work function of the gate electrode for the pMOS transistor, and it may be impossible to obtain a proper threshold value.
In order to overcome this problem, a dual metal gate has been proposed in which metallic materials are selected individually for the gate electrode of the nMOS transistor and the gate electrode of the pMOS transistor; for example, a metallic material having a work function comparable to that of n-type polysilicon is adopted for the gate electrode of the nMOS transistor and a metallic material having a work function comparable to that of p-type polysilicon is adopted for the gate electrode of the pMOS transistor (refer to, for example, Japanese Patent Laid-open Nos. 2003-258121 and 2003-45995).
Now, a method of producing a transistor with a dual metal gate electrode according to the related art will be described below, referring to manufacturing step sectional diagrams shown in FIGS. 6A to 6I.
First, as shown in FIG. 6A, trenches 112 and 113 for forming metal gates are formed in a layer insulation film 111 formed on a substrate, by a lithography technique and a dry etching technique. The layer insulation film 111 is composed, for example, of a silicon oxide film.
Next, as shown in FIG. 6B, a gate insulation film 121 and a metal gate material layer 122 for a pMOS transistor are formed on the whole surface of the layer insulation film 111 inclusive of the inside surfaces of the trenches 112, 113. The gate insulation film 121 in a thickness of, for example, several micrometers, and the metal gate material layer 122 is formed of a pMOS metal gate material in a thickness of about 10 to 40 nm. Incidentally, the substrate 11 portion is omitted in FIGS. 6B to 6I.
Subsequently, as shown in FIG. 6C, a resist is applied to the whole upper surface of the metal gate material layer 122 (the whole upper surface of the substrate), to form a resist film 123.
Next, as shown in FIG. 6D, an opening portion 124 is formed in the resist film 123 on the upper side of an nMOS transistor forming region, by a lithography technique. In this case, the resist film 122 is left on the upper side of a pMOS transistor forming region.
Subsequently, as shown in FIG. 6E, with the resist film 123 as an etching mask, the metal gate material layer 122 for the pMOS transistor in the nMOS transistor forming region is selectively etched by use of a chemical liquid. As a result, the metal gate material layer 122 for the pMOS transistor is left in the pMOS transistor forming region.
Next, the resist film 123 is removed by use of an organic solvent. As a result, the metal gate material layer 122 for the pMOS transistor is exposed, as shown in FIG. 6F.
Subsequently, as shown in FIG. 6G, a metal gate material layer 125 for the nMOS transistor is formed to cover the metal gate material layer 122 and to cover the whole surface of the layer insulation film 111 inclusive of the inside surfaces of the trenches 112, 113. The metal gate material layer 125 is formed of an nMOS metal gate material in a thickness of 10 to 40 nm, for example.
Next, as shown in FIG. 6H, an electrode metallic material layer 126 is formed on the metal gate material layer 125 for the nMOS transistor inclusive of the inside surfaces of the trenches 112, 113.
Subsequently, as shown in FIG. 6I, surplus portions of the electrode metallic material layer 126, the metal gate material layer 125 for the nMOS transistor and the metal gate material layer 122 for the pMOS transistor on the layer insulation film 111 are removed by chemical mechanical polishing (hereinafter abridged as CMP), whereby a metal gate 131 having the metal gate material layers 122, 125 and the electrode metallic material layer 126 embedded in the trench 112 with the gate insulation film 121 therebetween is formed, and a metal gate 132 having the metal gate material layer 125 for the pMOS transistor and the electrode metallic material layer 126 embedded in the trench 113 with the gate insulation film 121 therebetween is formed. In this manner, a dual gate structure including the metal gates is formed.